1. Field of the Invention
The present invention relates to a simulation method and apparatus for a circuit and, more particularly, to a circuit simulation method and apparatus for performing a circuit simulation by extracting resistances and capacitances from the layout data of a semiconductor integrated circuit.
2. Description of the Prior Art
An analog/digital hybrid circuit including a CMOS digital circuit such as a gate array, a cell base, or a microprocessor and an analog circuit is known. These circuits are integrated and commercially available as an LSI having a very high operating speed and a clock frequency of 200 MHz or more.
The characteristics of such a high-speed LSI cannot be satisfactorily evaluated by a circuit test at the time of circuit design. For this reason, layout data obtained after a layout process is used to extract interconnection resistive elements and interconnection capacitive elements included in signal interconnections and power supply interconnections, overlap capacitances which are physically present between the interconnections, capacitances between the adjacent interconnections, parasitic resistive/capacitive elements between device elements on the circuit, such as transistors, diodes, and resistive/capacitive elements between the interconnections, in addition to information about the device elements themselves. With this operation, circuit connection information including these parasitic elements is generated. A circuit simulation is performed by using this circuit data. In this manner, the circuit characteristics are evaluated at a level close to that for an actual circuit.
Conventionally, in most cases, such parasitic elements present in a circuit are extracted manually from a layout. Recently, however, with advances in automation of design by means of CAD tools, design can be performed at higher speeds as compared with manual design. In addition, automatic extraction has greatly improved extraction precision without artificial errors. Furthermore, with improvements in extraction models, for example, the capacitances between adjacent interconnections can be calculated with a high precision. This technique can therefore be satisfactorily applied to the most advanced process.
As described above, extraction of parasitic elements on a silicon substrate has attained a level at which no problem is posed in terms of speed and precision as compared with conventional manual extraction. However, parasitic elements present in a silicon substrate, e.g., the parasitic resistive/capacitive elements between the sub-terminals of MOS transistors and parasitic resistive/capacitive elements between well contact/sub-contact interconnections and the sub-terminals of the transistors, are still extracted roughly by a conventional manual extraction method.
With the recent decreases in element size and power supply voltage, the width of the operating voltage of each device element has reduced. For this reason, a circuit must be designed with sufficient consideration given to external noise. However, since almost no consideration is given to the influences of variations in transistor operation due to variations in voltage at the sub-terminal of each transistor which are caused by leakage of noise from a substrate, the influences of variations in the values of resistive and capacitive elements, and the influences of parasitic elements in the silicon substrate and well regions, these element greatly influence the circuit characteristics.
In addition, since clock synchronous circuits have become mainstream as digital LSIs, the influences of power supply voltage variations due to a clock operation on the sub-terminal of each transistor element on a circuit through well contact/sub-contact interconnections cannot be neglected either.
In a CMOS LSI including an analog circuit, a bias voltage is adjusted to compensate for reductions in Gm and drain current in each transistor, thereby realizing desired circuit characteristics. For this reason, a deterioration in performance of a silicon substrate or a well region due to parasitic elements becomes a factor that greatly influences the circuit characteristics.
An analog/digital hybrid LSI, in particular, exhibits a typical phenomenon in which noise from a digital portion leaks into an analog portion through a silicon substrate. For this reason, desired circuit characteristics cannot be apparently obtained.
To solve the above problems, modeling and extraction of parasitic elements in a silicon substrate and well regions and modeling and extraction of parasitic elements which are physically present between well contact/sub-contact interconnections and the sub-terminals of transistors must be accurately automated.
As described above, the problem of noise below the upper surface of a silicon substrate, which has become a noticeable factor that influences circuit characteristics with decreases in element size and power supply voltage, is scarcely solved because techniques of modeling and extracting parasitic elements associated with a silicon substrate and well regions have not been established. Since a circuit test is performed by rough manual estimation, a serious problem is posed in the future LSI design.
According to a conventional manual parasitic element estimation technique, a skilled designer estimates parasitic elements from information about the position of each element and element size information of the layout data of a circuit on the basis of his or her knowledge and the past know-how in design. The extraction precision therefore greatly depends on the experience and skill of the designer. In addition, as the circuit size increases, the number of steps in extraction increases, and artificial errors tend to occur.
In an analog circuit, even if the relative positions of transistors on a layout are spaced apart from each other, the transistors having high performance generate large amounts of noise and influence each other. To prevent this, certain distances are generally ensured between these elements. In this case, however, since noise is not quantitatively estimated, relative distances larger than the optimal inter-element distances are ensured. As a result, the layout size undesirably increases.